It is frequently desirable to include an electrically erasable programmable read-only-memory (EEPROM) in an integrated circuit (IC) chip. Examples are the "smart" analog chips used in antilock braking systems (ABS) and in data converters having an EEPROM-trimming architecture. Such chips typically contain a number of CMOS transistors as well as select transistors and memory transistors for the EEPROM cells. The memory transistors may include a single or double polysilicon layer.
A problem in the fabrication of these devices has been the large number of additional process steps, particularly masking steps, which are necessary in the fabrication of EEPROMs. An EEPROM fabricated with a single conductive (polysilicon) layer minimizes the number of extra processing steps, but this solution comes at the cost of an increased cell size. The density of double polysilicon layer EEPROM cells is typically greater than the density of single polysilicon layer EEPROM cells. In addition, use of two polysilicon layers allows the designer to include interpoly capacitors on the chip. High performance interpoly capacitors are particularly useful in the fabrication of data converters and precision capacitor circuits.
Another problem arises from the continuing reduction in the size of the CMOS devices. An EEPROM is normally programmed at a voltage of 15-17 V. With a 2.0 .mu.m CMOS technology, the gate oxides and junctions of the CMOS devices are generally capable of withstanding such voltages. As the CMOS technology approaches the 1.0 .mu.m scale, however, the CMOS transistors are not able to withstand the relatively high voltages necessary to program and erase the EEPROM cells. Accordingly, chips which contain extremely small scale logic devices typically have separate high voltage transistors to perform the bit line select gate function and otherwise interface with the EEPROM memory transistors. This adds more complexity to the fabrication process.